/** \file compiler_defs.h
 *
 * \brief Register/bit definitions for cross-compiler projects on the C8051F93x/2x family.
 *
 * \b COPYRIGHT
 * \n Portions of this file are copyright Maarten Brock
 * \n http://sdcc.sourceforge.net
 * \n Portions of this file are copyright 2010, Silicon Laboratories, Inc.
 * \n http://www.silabs.com
 *
 *
 * <b> GNU LGPL boilerplate: </b>
 * \n This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 * \n This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
 * Lesser General Public License for more details.
 * \n You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 * \n In other words, you are welcome to use, share and improve this program.
 * You are forbidden to forbid anyone else to use, share and improve
 * what you give them. Help stamp out software-hoarding!
 *
 * <b> Program Description: </b>
 * \note This header file should be included before including
 * a device-specific header file such as C8051F300_defs.h.
 *
 * Macro definitions to accommodate 8051 compiler differences in specifying
 * special function registers and other 8051-specific features such as NOP
 * generation, and locating variables in memory-specific segments.  The
 * compilers are identified by their unique predefined macros. See also:
 * http://predef.sourceforge.net/precomp.html
 *
 * SBIT and SFR define special bit and special function registers at the given
 * address. SFR16 and SFR32 define sfr combinations at adjacent addresses in
 * little-endian format. SFR16E and SFR32E define sfr combinations without
 * prerequisite byte order or adjacency. None of these multi-byte sfr
 * combinations will guarantee the order in which they are accessed when read
 * or written.
 *
 * SFR16X and SFR32X for 16 bit and 32 bit xdata registers are not defined
 * to avoid portability issues because of compiler endianness.
 *
 * Example:
 * \code
 * // my_mcu.c: main 'c' file for my mcu
 * #include <compiler_defs.h>  // this file
 * #include <C8051xxxx_defs.h> // SFR definitions for specific MCU target
 *
 * SBIT  (P0_1, 0x80, 1);      // Port 0 pin 1
 * SFR   (P0, 0x80);           // Port 0
 * SFRX  (CPUCS, 0xE600);      // Cypress FX2 Control and Status register in
 *                             // xdata memory at 0xE600
 * SFR16 (TMR2, 0xCC);         // Timer 2, lsb at 0xCC, msb at 0xCD
 * SFR16E(TMR0, 0x8C8A);       // Timer 0, lsb at 0x8A, msb at 0x8C
 * SFR32 (MAC0ACC, 0x93);      // SiLabs C8051F120 32 bits MAC0 Accumulator,
 *                             // lsb at 0x93, msb at 0x96
 * SFR32E(SUMR, 0xE5E4E3E2);   // TI MSC1210 SUMR 32 bits Summation register,
 *                             // lsb at 0xE2, msb at 0xE5
 * \endcode
 *
 * <b>Target:</b>         C8051xxxx
 * \n <b>Tool chain:</b>     Generic
 * \n <b>Command Line:</b>   None
 *
 * Release 2.3 - 27 MAY 2010 (DM)
 * \n    -Removed 'LOCATED_VARIABLE' pragma from Keil because it is not supported
 * \n Release 2.2 - 06 APR 2010 (ES)
 * \n    -Removed 'PATHINCLUDE' pragma from Raisonance section
 * \n Release 2.1 - 16 JUL 2009 (ES)
 * \n    -Added SEGMENT_POINTER macro definitions for SDCC, Keil, and Raisonance
 * \n    -Added LOCATED_VARIABLE_NO_INIT macro definitions for Raisonance
 * \n Release 2.0 - 19 MAY 2009 (ES)
 * \n    -Added LOCATED_VARIABLE_NO_INIT macro definitions for SDCC and Keil
 * \n Release 1.9 - 23 OCT 2008 (ES)
 * \n    -Updated Hi-Tech INTERRUPT and INTERRUPT_USING macro definitions
 * \n    -Added SFR16 macro defintion for Hi-Tech
 * \n Release 1.8 - 31 JUL 2008 (ES)
 * \n    -Added INTERRUPT_USING and FUNCTION_USING macro's
 * \n    -Added macro's for IAR
 * \n    -Corrected Union definitions for Hi-Tech and added SFR16 macro defintion
 * \n Release 1.7 - 11 SEP 2007 (BW)
 * \n    -Added support for Raisonance EVAL 03.03.42 and Tasking Eval 7.2r1
 * \n Release 1.6 - 27 AUG 2007 (BW)
 * \n    -Updated copyright notice per agreement with Maartin Brock
 * \n    -Added SDCC 2.7.0 "compiler.h" bug fixes
 * \n    -Added memory segment defines (SEG_XDATA, for example)
 * \n Release 1.5 - 24 AUG 2007 (BW)
 * \n    -Added support for NOP () macro
 * \n    -Added support for Hi-Tech ver 9.01
 * \n Release 1.4 - 07 AUG 2007 (PKC)
 * \n    -Removed FID and fixed formatting.
 * \n Release 1.3 - 30 SEP 2007 (TP)
 * \n    -Added INTERRUPT_PROTO_USING to properly support ISR context switching
 *      under SDCC.
 * \n Release 1.2 - (BW)
 * \n    -Added support for U8,U16,U32,S8,S16,S32,UU16,UU32 data types
 * \n Release 1.1 - (BW)
 * \n    -Added support for INTERRUPT, INTERRUPT_USING, INTERRUPT_PROTO,
 *      SEGMENT_VARIABLE, VARIABLE_SEGMENT_POINTER,
 *      SEGMENT_VARIABLE_SEGMENT_POINTER, and LOCATED_VARIABLE
 * \n Release 1.0 - 29 SEP 2006 (PKC)
 * \n    -Initial revision
 */

//-----------------------------------------------------------------------------
// Header File Preprocessor Directive
//-----------------------------------------------------------------------------

#ifndef COMPILER_DEFS_H
#define COMPILER_DEFS_H
#include <unistd.h>

#include "radio.h"
#include "radio_config.h"
#include "radio_comm.h"
#include "si446x_api_lib.h"
#include "si446x_defs.h"

#define SEG_GENERIC
#define SEG_FAR  // __xdata
#define SEG_DATA  //__data
#define SEG_NEAR // __data
#define SEG_IDATA //__idata
#define SEG_XDATA //__xdata
#define SEG_PDATA //__pdata
#define SEG_CODE  //__code
//# define SEG_BDATA __bdata

#define SBIT(name, addr, bit)  //__sbit  __at(addr+bit)                  name
#define SFR(name, addr)        //__sfr   __at(addr)                      name
#define SFRX(name, addr)      // xdata volatile unsigned char __at(addr) name
#define SFR16(name, addr)      //__sfr16 __at(((addr+1U)<<8) | addr)     name
#define SFR16E(name, fulladdr) //__sfr16 __at(fulladdr)                  name
#define SFR32(name, addr)      //__sfr32 __at(((addr+3UL)<<24) | ((addr+2UL)<<16) | ((addr+1UL)<<8) | addr) name
#define SFR32E(name, fulladdr) //__sfr32 __at(fulladdr)                  name
#define FALSE 0
#define TRUE  1


// used with UU16
#define LSB 0
#define MSB 1

// used with UU32 (b0 is least-significant byte)
#define b0 0
#define b1 1
#define b2 2
#define b3 3


#define gpio_base            		0xf1c20800

#define PA_CFG0_REG        			(gpio_base+0x000)  //0xf1c20800
#define PA_CFG1_REG           	    (gpio_base+0x004)
#define PA_CFG2_REG         		(gpio_base+0x008)
#define PA_CFG3_REG         		(gpio_base+0x00C)
#define PA_DAT_REG         			(gpio_base+0x010)
#define PA_DRV0_REG        			(gpio_base+0x014)
#define PA_DRV1_REG        			(gpio_base+0x018)
#define PA_PULL0_REG     			(gpio_base+0x01C)
#define PA_PULL1_REG     			(gpio_base+0x020)
#define PB_CFG0_REG        			(gpio_base+0x024)
#define PB_CFG1_REG           	    (gpio_base+0x028)
#define PB_CFG2_REG         		(gpio_base+0x02C)
#define PB_CFG3_REG         		(gpio_base+0x030)
#define PB_DAT_REG         			(gpio_base+0x034)
#define PB_DRV0_REG        			(gpio_base+0x038)
#define PB_DRV1_REG        			(gpio_base+0x03C)
#define PB_PULL0_REG     			(gpio_base+0x040)
#define PB_PULL1_REG     			(gpio_base+0x044)
#define PC_CFG0_REG        			(gpio_base+0x048)
#define PC_CFG1_REG           	    (gpio_base+0x04C)
#define PC_CFG2_REG         		(gpio_base+0x050)
#define PC_CFG3_REG         		(gpio_base+0x054)
#define PC_DAT_REG         			(gpio_base+0x058)
#define PC_DRV0_REG        			(gpio_base+0x05C)
#define PC_DRV1_REG        			(gpio_base+0x060)
#define PC_PULL0_REG     			(gpio_base+0x064)
#define PC_PULL1_REG     			(gpio_base+0x068)
#define PD_CFG0_REG        			(gpio_base+0x06C)
#define PD_CFG1_REG           	    (gpio_base+0x070)
#define PD_CFG2_REG         		(gpio_base+0x074)
#define PD_CFG3_REG         		(gpio_base+0x078)
#define PD_DAT_REG         			(gpio_base+0x07C)
#define PD_DRV0_REG        			(gpio_base+0x080)
#define PD_DRV1_REG        			(gpio_base+0x084)
#define PD_PULL0_REG     			(gpio_base+0x088)
#define PD_PULL1_REG     			(gpio_base+0x08C)
#define PE_CFG0_REG        			(gpio_base+0x090)
#define PE_CFG1_REG           	    (gpio_base+0x094)
#define PE_CFG2_REG         		(gpio_base+0x098)
#define PE_CFG3_REG         		(gpio_base+0x09C)
#define PE_DAT_REG         			(gpio_base+0x0A0)
#define PE_DRV0_REG        			(gpio_base+0x0A4)
#define PE_DRV1_REG        			(gpio_base+0x0A8)
#define PE_PULL0_REG     			(gpio_base+0x0AC)
#define PE_PULL1_REG     			(gpio_base+0x0B0)
#define PF_CFG0_REG        			(gpio_base+0x0B4)
#define PF_CFG1_REG           	    (gpio_base+0x0B8)
#define PF_CFG2_REG         		(gpio_base+0x0BC)
#define PF_CFG3_REG         		(gpio_base+0x0C0)
#define PF_DAT_REG         			(gpio_base+0x0C4)
#define PF_DRV0_REG        			(gpio_base+0x0C8)
#define PF_DRV1_REG        			(gpio_base+0x0CC)
#define PF_PULL0_REG     			(gpio_base+0x0D0)
#define PF_PULL1_REG     			(gpio_base+0x0D4)
#define PG_CFG0_REG        			(gpio_base+0x0D8)
#define PG_CFG1_REG           	    (gpio_base+0x0DC)
#define PG_CFG2_REG         		(gpio_base+0x0E0)
#define PG_CFG3_REG         		(gpio_base+0x0E4)
#define PG_DAT_REG         			(gpio_base+0x0E8)
#define PG_DRV0_REG        			(gpio_base+0x0EC)
#define PG_DRV1_REG        			(gpio_base+0x0F0)
#define PG_PULL0_REG     			(gpio_base+0x0F4)
#define PG_PULL1_REG     			(gpio_base+0x0F8)
#define PH_CFG0_REG         		(gpio_base+0x0FC)
#define PH_CFG1_REG           	    (gpio_base+0x100)
#define PH_CFG2_REG         		(gpio_base+0x104)
#define PH_CFG3_REG         		(gpio_base+0x108)
#define PH_DAT_REG         		    (gpio_base+0x10C)
#define PH_DRV0_REG        		    (gpio_base+0x110)
#define PH_DRV1_REG        		    (gpio_base+0x114)
#define PH_PULL0_REG     			(gpio_base+0x118)
#define PH_PULL1_REG     			(gpio_base+0x11C)
#define PI_CFG0_REG         		(gpio_base+0x120)
#define PI_CFG1_REG           	    (gpio_base+0x124)
#define PI_CFG2_REG         		(gpio_base+0x128)
#define PI_CFG3_REG         		(gpio_base+0x12C)
#define PI_DAT_REG         		    (gpio_base+0x130)
#define PI_DRV0_REG        		    (gpio_base+0x134)
#define PI_DRV1_REG        		    (gpio_base+0x138)
#define PI_PULL0_REG     			(gpio_base+0x13C)
#define PI_PULL1_REG     			(gpio_base+0x140) 

extern unsigned int memRead(unsigned int addr)  ;
extern void memWrite( unsigned int addr, int value)  ;

extern void SPI_WRITE_BIT( int valueBit, int value) ;


/*
          rx                                tx(develop board)
SDN   3   PA9(CKO2)                     	PG0(PCLK)

NSEL  4   PA5(SPI3_CS0)                 	PG2(HSYNC)

SCK   5   PA6(SPI3_CLK)                 	PG4(D0)

SDI   6   PA7(SPI3_MOSI)                 	PG6(D2)

SD0   8   PA8(SPI3_MISO)   input           	PG8(D4)

NIRQ  7   PB10             input           	PG10(D6)

*/

#ifdef CORE_BOARD   //#defined in radio.h

//  mainBoard
#define SPI_SDN(value)   SPI_WRITE_BIT (  9, value )   //PA_DAT_REG
#define SPI_SEL(value)   SPI_WRITE_BIT (  5, value ) 
#define SPI_SCL(value)   SPI_WRITE_BIT (  6, value ) 
#define SPI_SDI(value)   SPI_WRITE_BIT (  7, value )  
#define Sdo_Data ( memRead(PA_DAT_REG) & (1 << 8) )
#define SPI_IRQ  ( memRead(PB_DAT_REG) & (1 << 10) ) 
#else
// develop board	
#define SPI_SDN(value)   SPI_WRITE_BIT (  0, value )  //PG_DAT_REG
#define SPI_SEL(value)   SPI_WRITE_BIT (  2, value ) 
#define SPI_SCL(value)   SPI_WRITE_BIT (  4, value ) 
#define SPI_SDI(value)   SPI_WRITE_BIT (  6, value )  
#define Sdo_Data ( memRead(PG_DAT_REG) & (1 << 8) )
#define SPI_IRQ  ( memRead(PG_DAT_REG) & (1 << 10) ) 

#endif


						
#define nSEL_Hi()  SPI_SEL(1)
#define nSEL_Low() SPI_SEL(0) 
						
#define Sdi_Hi()  SPI_SDI(1)
#define Sdi_Low() SPI_SDI(0)
						
#define Wait_Sdo_Hi() while(Sdo_Data == 0)
						
#define Sck_Hi()  SPI_SCL(1)
#define Sck_Low() SPI_SCL(0)
						
						
#define radio_hal_AssertShutdown() 		SPI_SDN(1)
#define radio_hal_DeassertShutdown() 	SPI_SDN(0)
#define radio_hal_ClearNsel()             SPI_SEL(0)
#define radio_hal_SetNsel()  				SPI_SEL(1)
#define radio_hal_NirqLevel()				SPI_IRQ


#endif                                 // #define COMPILER_DEFS_H

//-----------------------------------------------------------------------------
// End Of File
//-----------------------------------------------------------------------------
